![]() Note that the STM32 DSI host is capable of halting transmission, i.e. Ultimately, depending on the timing parameters specified in the LCD display datasheet, the maximum resolution and frame rate can be determined and it strongly depends on the display controller. ![]() If there is, the display benefits from having a frame buffer. It is up to you to negotiate and decide that with the display attached to the DSI host.Īlso, because control traffic is also carried by the MIPI DSI interface itself, you have to make sure that there is no significant control traffic interrupting the graphic data stream. The MIPI Alliance specifications do not specify a maximum resolution or frame rate. This clock pair can put out a maximum clock rate of 500 MHz, which results in the data lanes (DATA0 and DATA1 pairs) shifting out data at 1 Gbps each. Every STM32 that features a MIPI DSI host has a pair of differential clock lines (CLK0_P and CLK0_N).
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